View ADN4663_5006804.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Dual, 3 V, CMOS, LVDS High Speed Differential Driver ADN4663
FEATURES
15 kV ESD protection on output pins 600 Mbps (300 MHz) switching rates Flow-through pinout simplifies PCB layout 300 ps typical differential skew 700 ps maximum differential skew 1.5 ns maximum propagation delay 3.3 V power supply 355 mV differential signaling Low power dissipation: 23 mW typical Interoperable with existing 5 V LVDS receivers Conforms to TIA/EIA-644 LVDS standard Industrial operating temperature range (-40C to +85C) Available in surface-mount (SOIC) package
FUNCTIONAL BLOCK DIAGRAM
VCC
ADN4663
DIN1 DOUT1+ DOUT1-
DIN2
DOUT2+ DOUT2-
07927-001
GND
Figure 1.
APPLICATIONS
Backplane data transmission Cable data transmission Clock distribution
GENERAL DESCRIPTION
The ADN4663 is a dual, CMOS, low voltage differential signaling (LVDS) line driver offering data rates of over 600 Mbps (300 MHz), and ultralow power consumption. It features a flow-through pinout for easy PCB layout and separation of input and output signals. The device accepts low voltage TTL/CMOS logic signals and converts them to a differential current output of typically 3.1 mA for driving a transmission medium such as a twisted-pair cable. The transmitted signal develops a differential voltage of typically 355 mV across a termination resistor at the receiving end, and this is converted back to a TTL/CMOS logic level by a line receiver. The ADN4663 and a companion receiver offer a new solution to high speed point-to-point data transmission, and a low power alternative to emitter-coupled logic (ECL) or positive emitter-coupled logic (PECL).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
ADN4663 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 AC Characteristics........................................................................ 4 Absolute Maximum Ratings............................................................ 6 ESD Caution...................................................................................6 Pin Configuration and Function Descriptions..............................7 Typical Performance Characteristics ..............................................8 Theory of Operation ...................................................................... 11 Applications Information .......................................................... 11 Outline Dimensions ....................................................................... 12 Ordering Guide .......................................................................... 12
REVISION HISTORY
1/09--Revision 0: Initial Version
Rev. 0 | Page 2 of 12
ADN4663 SPECIFICATIONS
VCC = 3.0 V to 3.6 V; RL = 100 ; CL = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 1.
Parameter 1, 2 LVDS OUTPUTS (DOUTx+, DOUTx-) Differential Output Voltage Change in Magnitude of VOD for Complementary Output States Offset Voltage Change in Magnitude of VOS for Complementary Output States Output High Voltage Output Low Voltage INPUTS (DIN1, DIN2) Input High Voltage Input Low Voltage Input High Current Input Low Current Input Clamp Voltage LVDS OUTPUT PROTECTION (DOUTx+, DOUTx-) Output Short-Circuit Current 3 LVDS OUTPUT LEAKAGE (DOUTx+, DOUTx-) Power-Off Leakage POWER SUPPLY Supply Current, Unloaded Supply Current, Loaded ESD PROTECTION DOUTx+, DOUTx- Pins All Pins Except DOUTx+, DOUTx-
1 2
Symbol VOD VOD VOS VOS VOH VOL VIH VIL IIH IIL VCL IOS IOFF ICC ICCL
Min 250
Typ 355 1 1.2 3 1.4 1.1
Max 450 35 1.375 25 1.6
Unit mV |mV| V |mV| V V V V A A V mA A mA mA kV kV
Test Conditions See Figure 2 and Figure 4 See Figure 2 and Figure 4 See Figure 2 and Figure 4 See Figure 2 and Figure 4 See Figure 2 and Figure 4 See Figure 2 and Figure 4
1.125
0.90 2.0 GND -10 -10 -1.5
2 1 -0.6 -5.7
VCC 0.8 +10 +10
VIN = 3.3 V or 2.4 V VIN = GND or 0.5 V ICL = -18 mA DINx = VCC, DOUTx+ = 0 V or DINx = GND, DOUTx- = 0 V VOUT = VCC or GND, VCC = 0 V No load, DINx = VCC or GND DINx = VCC or GND Human body model Human body model
-8.0 +10 14 20
-10
1 8 10 15 4
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD, VOD, and VOS. The ADN4663 is a current mode device and functions within data sheet specifications only when a resistive load is applied to the driver outputs. Typical range is 90 to 110 . 3 Output short-circuit current (IOS) is specified as magnitude only; minus sign indicates direction only.
Rev. 0 | Page 3 of 12
ADN4663
AC CHARACTERISTICS
VCC = 3.0 V to 3.6 V; RL = 100 ; CL 1 = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
Parameter 2 Differential Propagation Delay High to Low Differential Propagation Delay Low to High Differential Pulse Skew |tPHLD - tPLHD| 5 Channel-to-Channel Skew 6 Differential Part-to-Part Skew 7 Differential Part-to-Part Skew 8 Rise Time Fall Time Maximum Operating Frequency 9
1 2 3
Symbol tPHLD tPLHD tSKD1 tSKD2 tSKD3 tSKD4 tTLH tTHL fMAX
Min 0.3 0.3 0 0 0 0 0.2 0.2
Typ 0.8 1.1 0.3 0.4
0.5 0.5 350
Max 1.5 1.5 0.7 0.8 1.0 1.2 1.0 1.0
Unit ns ns ns ns ns ns ns ns MHz
Conditions/Comments 3, 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3
CL includes probe and jig capacitance. AC parameters are guaranteed by design and characterization. Generator waveform for all tests, unless otherwise specified: f = 50 MHz, ZO = 50 , tTLH 1 ns, and tTHL 1 ns. 4 All input voltages are for one channel, unless otherwise specified. Other inputs are set to GND. 5 tSKD1 = |tPHLD - tPLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. 6 tSKD2 is the differential channel-to-channel skew of any event on the same device. 7 tSKD3, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5C of each other within the operating temperature range. 8 tSKD4, differential part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating temperatures and voltage ranges, and across process distribution. tSKD4 is defined as |maximum - minimum| differential propagation delay. 9 fMAX generator input conditions: tTLH = tTHL < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%, VOD > 250 mV, all channels switching.
Rev. 0 | Page 4 of 12
ADN4663
Test Circuits and Timing Diagrams
VCC DOUTx+
VCC DINx
RL/2
V
VOS
RL/2 DOUTx-
V
VOD
07927-002
Figure 2. Test Circuit for Driver VOD and VOS
VCC
CL SIGNAL GENERATOR DINx 50 CL CL INCLUDES LOAD AND TEST JIG CAPACITANCE. RL
DOUTx+
DOUTx-
07927-003
Figure 3. Test Circuit for Driver Propagation Delay, Transition Time, and Maximum Operating Frequency
3V DINx 1.5V
1.5V
0V
tPLHD
DOUTx- 0V (DIFFERENTIAL) VOD DOUTx+
tPHLD
VOH 0V VOL
80% VDIFF 20% 0V VDIFF = DOUT+ - DOUT-
80% 0V 20%
tTHL
tTHL
Figure 4. Driver Propagation Delay and Transition Time Waveforms
Rev. 0 | Page 5 of 12
07927-004
ADN4663 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. All voltages are relative to their respective ground. Table 3.
Parameter VCC to GND Input Voltage (DINx) to GND Output Voltage (DOUTx+, DOUTx-) to GND Short-Circuit Duration (DOUTx+, DOUTx-) to GND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) Power Dissipation SOIC Package JA Thermal Impedance Reflow Soldering Peak Temperature Pb-Free Rating -0.3 V to +4 V -0.3 V to VCC + 0.3 V -0.3 V to VCC + 0.3 V Continuous -40C to +85C -65C to +150C 150C (TJ max - TA)/JA 149.5C/W 260C 5C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. 0 | Page 6 of 12
ADN4663 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VCC DIN1 DIN2 GND
1 2 3 4 8
DOUT1- DOUT1+ DOUT2-
07927-005
ADN4663
TOP VIEW (Not to Scale)
7 6 5
DOUT2+
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 Mnemonic VCC DIN1 DIN2 GND DOUT2- DOUT2+ DOUT1+ DOUT1- Description Power Supply Input. The part can be operated from 3.0 V to 3.6 V, and the supply should be decoupled with a 10 F solid tantalum capacitor in parallel with a 0.1 F capacitor to GND. Driver Channel 1 Logic Input. Driver Channel 2 Logic Input. Ground reference point for all circuitry on the part. Channel 2 Inverting Output Current Driver. When DIN2 is high, current flows into DOUT2-. When DIN2 is low, current flows out of DOUT2-. Channel 2 Noninverting Output Current Driver. When DIN2 is high, current flows out of DOUT2+. When DIN2 is low, current flows into DOUT2+. Channel 1 Noninverting Output Current Driver. When DIN1 is high, current flows out of DOUT1+. When DIN1 is low, current flows into DOUT1+. Channel 1 Inverting Output Current Driver. When DIN1 is high, current flows into DOUT1-. When DIN1 is low, current flows out of DOUT1-.
Rev. 0 | Page 7 of 12
ADN4663 TYPICAL PERFORMANCE CHARACTERISTICS
1.415 DIFFERENTIAL OUTPUT VOLTAGE, VOD (mV) TA = 25C RL = 100
325.0 TA = 25C RL = 100
OUTPUT HIGH VOLTAGE, VOH (V)
324.8
1.414
324.6
324.4
1.413
324.2
3.1
3.2
3.3
3.4
3.5
3.6
3.1
3.2
3.3
3.4
3.5
3.6
POWER SUPPLY VOLTAGE, VCC (V)
POWER SUPPLY VOLTAGE, VCC (V)
Figure 6. Output High Voltage vs. Power Supply Voltage
Figure 9. Differential Output Voltage vs. Power Supply Voltage
1.090
DIFFERENTIAL OUTPUT VOLTAGE, VOD (mV)
TA = 25C RL = 100
500
TA = 25C VCC = 3.3V
OUTPUT LOW VOLTAGE, VOL (V)
450
1.089
400
350
1.088
300
07927-007
3.1
3.2
3.3
3.4
3.5
3.6
90
100
110
120
130
140
150
POWER SUPPLY VOLTAGE, VCC (V)
LOAD RESISTOR, RL ()
Figure 7. Output Low Voltage vs. Power Supply Voltage
Figure 10. Differential Output Voltage vs. Load Resistor
-3.9 TA = 25C VIN = GND OR VCC VOUT = 0V
1.252
TA = 25C RL = 100
SHORT-CIRCUIT CURRENT, I OS (mA)
OFFSET VOLTAGE, VOS (mV)
-4.0
1.251
-4.1
1.250
07927-008
3.1
3.2
3.3
3.4
3.5
3.6
3.1
3.2
3.3
3.4
3.5
3.6
POWER SUPPLY VOLTAGE, VCC (V)
POWER SUPPLY VOLTAGE, VCC (V)
Figure 8. Output Short-Circuit Current vs. Power Supply Voltage
Figure 11. Offset Voltage vs. Power Supply Voltage
Rev. 0 | Page 8 of 12
07927-011
-4.2 3.0
1.249 3.0
07927-010
1.087 3.0
250
07927-009
07927-006
1.412 3.0
324.0 3.0
ADN4663
TA = 25C CL = 15pF VCC = 3.3V VIN = 0V TO 3.3V RL = 100 PER DRIVER BOTH CHANNELS SWITCHING
1200
DIFFERENTIAL PROPAGATION DELAY (ns)
19
POWER SUPPLY CURRENT, ICC (mA)
17 15 13 11 9 7
TA = 25C f = 1MHz CL = 15pF RL = 100 PER DRIVER
1100
tPHLD tPLHD
ONE CHANNEL SWITCHING
1000
07927-012
0.1
1
10
100
1k
3.1
3.2
3.3
3.4
3.5
3.6
SWITCHING FREQUENCY (MHz)
POWER SUPPLY VOLTAGE, VCC (V)
Figure 12. Power Supply Current vs. Switching Frequency
Figure 15. Differential Propagation Delay vs. Power Supply Voltage
12.5
12.0
DIFFERENTIAL PROPAGATION DELAY (ns)
POWER SUPPLY CURRENT, ICC (mA)
TA = 25C f = 1MHz CL = 15pF VIN = 0V TO 3.3V RL = 100 PER DRIVER
1200
VCC = 3.3V f = 1MHz CL = 15pF RL = 100 PER DRIVER tPLHD
1100
11.5
11.0
tPHLD 1000
10.5
07927-013
3.1
3.2
3.3
3.4
3.5
3.6
-20
0
20
40
60
80
100
POWER SUPPLY VOLTAGE, VCC (V)
AMBIENT TEMPERATURE, TA (C)
Figure 13. Power Supply Current vs. Power Supply Voltage
Figure 16. Differential Propagation Delay vs. Ambient Temperature
15
100
VCC = 3.3V f = 1MHz CL = 15pF VIN = 0V TO 3V RL = 100 PER DRIVER
POWER SUPPLY CURRENT, ICC (mA)
DIFFERENTIAL SKEW, tSKD1 (ps)
14
80
TA = 25C f = 1MHz CL = 15pF RL = 100 PER DRIVER
13
60
12
40
11
20
07927-014
-15
10
35
60
85
3.1
3.2
3.3
3.4
3.5
3.6
TEMPERATURE (C)
POWER SUPPLY VOLTAGE, VCC (V)
Figure 14. Power Supply Current vs. Ambient Temperature
Figure 17. Differential Skew vs. Power Supply Voltage
Rev. 0 | Page 9 of 12
07927-017
10 -40
0 3.0
07927-016
10.0 3.0
900 -40
07927-015
5 0.01
900 3.0
ADN4663
50 VCC = 3.3V f = 1MHz CL = 15pF RL = 100 PER DRIVER TRANSITION TIME (ps) 400 VCC = 3.3V f = 1MHz CL = 15pF RL = 100 PER DRIVER
DIFFERENTIAL SKEW, tSKD1 (ps)
40
380 tTLH 360 tTHL
30
20
10
340
07927-018
-20
0
20
40
60
80
100
-20
0
20
40
60
80
100
AMBIENT TEMPERATURE, TA (C)
AMBIENT TEMPERATURE, TA (C)
Figure 18. Differential Skew vs. Ambient Temperature
Figure 20. Transition Time vs. Ambient Temperature
400
TA = 25C f = 1MHz CL = 15pF RL = 100 PER DRIVER tTLH
TRANSITION TIME (ps)
380
360
tTHL
340
3.1
3.2
3.3
3.4
3.5
3.6
POWER SUPPLY VOLTAGE, VCC (V)
Figure 19. Transition Time vs. Power Supply Voltage
Rev. 0 | Page 10 of 12
07927-019
320 3.0
07927-020
0 -40
320 -40
ADN4663 THEORY OF OPERATION
The ADN4663 is a dual line driver for low voltage differential signaling. It takes a single-ended 3 V logic signal and converts it to a differential current output. The data can then be transmitted for considerable distances, over media such as a twisted-pair cable or PCB backplane, to an LVDS receiver, where it develops a voltage across a terminating resistor, RT. This resistor is chosen to match the characteristic impedance of the medium, typically around 100 . The differential voltage is detected by the receiver and converted back into a single-ended logic signal. When DINx is high (Logic 1), current flows out of the DOUTx+ pin (current source) through RT and back into the DOUTx- pin (current sink). At the receiver, this current develops a positive differential voltage across RT (with respect to the inverting input) and results in a Logic 1 at the receiver output. When DINx is low, DOUTx+ sinks current and DOUTx- sources current; a negative differential voltage across RT results in a Logic 0 at the receiver output. The output drive current is between 2.5 mA and 4.5 mA (typically 3.55 mA), developing between 250 mV and 450 mV across a 100 termination resistor. The received voltage is centered around the receiver offset of 1.2 V. Therefore, the noninverting receiver input is typically (1.2 V + [355 mV/2]) = 1.377 V, and the inverting receiver input is (1.2 V - [355 mV/2]) = 1.023 V for Logic 1. For Logic 0, the inverting and noninverting output voltages are reversed. Note that because the differential voltage reverses polarity, the peak-to-peak voltage swing across RT is twice the differential voltage. Current mode drivers offer considerable advantages over voltage mode drivers such as RS-422 drivers. The operating current remains fairly constant with increased switching frequency, whereas that of voltage mode drivers increase exponentially in most cases. This is caused by the overlap as internal gates switch between high and low, which causes currents to flow from the device power supply to ground. A current mode device simply reverses a constant current between its two outputs, with no significant overlap currents. This is similar to emitter-coupled logic (ECL) and positive emitter-coupled logic (PECL), but without the high quiescent current of ECL and PECL.
APPLICATIONS INFORMATION
Figure 21 shows a typical application for point-to-point data transmission using the ADN4663 as the driver and a LVDS receiver.
0.1F VCC +3.3V + 10F TANTALUM VCC
+
+3.3V
ADN4663
DINx
DOUTx+ DOUTx- RT 100
DIN+
DIN-
LVDS RECEIVER
DOUT
07927-021
GND
GND
Figure 21. Typical Application Circuit
Rev. 0 | Page 11 of 12
ADN4663 OUTLINE DIMENSIONS
5.00 (0.1968) 4.80 (0.1890)
4.00 (0.1574) 3.80 (0.1497)
8 1
5 4
6.20 (0.2441) 5.80 (0.2284)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) 0.25 (0.0099) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157)
45
0.51 (0.0201) 0.31 (0.0122)
COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 22. 8-Lead Standard Small Outline Package [SOIC(N)] (R-8) Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model ADN4663BRZ 1 ADN4663BRZ-REEL71
1
Temperature Range -40C to +85C -40C to +85C
Package Description 8-Lead Standard Small Outline Package [SOIC-N] 8-Lead Standard Small Outline Package [SOIC-N]
012407-A
Package Option R-8 R-8
Z = RoHS Compliant Part.
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07927-0-1/09(0)
Rev. 0 | Page 12 of 12

▲Up To Search▲

Price & Availability of ADN4663

	To Download ADN4663 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .